volume | PIER Journals

Abstract

In this paper, a 42 GHz frequency synthesizer fabricated with 0.13 μm SiGe BiCMOS technology is presented, which consists of an integer-N fourth-order type-II phase locked loop (PLL) with a LC tank VCO and a frequency doubler. The core PLL has three-stage current mode logic(CML) and five stage true single phase clock (TSPC) logic in the frequency divider. Meanwhile, a novel balanced common-base structure is used in the frequency doubler design to widen the bandwidth and improve the fundamental rejection. The doubler shows a 41% fractional 3 dB bandwidths with a fundamental rejection better than 25.7 dB. The synthesizer has a maximum output power of 0 dBm with a DC power consumption of 60 mW. The worst phase noise at 100 kHz, 1 MHz and 10 MHz offset frequencies from the carrier is -71 dBc/Hz, -83 dBc/Hz and -102.4 dBc/Hz, respectively.

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Mr. Jiankang Li

Dr. Yong-Zhong Xiong

Dr. Jin He

Dr. Wen Wu