Vol. 47

Front:[PDF file] Back:[PDF file]
Latest Volume
All Volumes
All Issues
2014-01-24

A Q-Band Frequency Synthesizer in 0.13 μm SiGe BiCMOS

By Jiankang Li, Yong-Zhong Xiong, Jin He, and Wen Wu
Progress In Electromagnetics Research C, Vol. 47, 19-28, 2014
doi:10.2528/PIERC13120408

Abstract

In this paper, a 42 GHz frequency synthesizer fabricated with 0.13 μm SiGe BiCMOS technology is presented, which consists of an integer-N fourth-order type-II phase locked loop (PLL) with a LC tank VCO and a frequency doubler. The core PLL has three-stage current mode logic(CML) and five stage true single phase clock (TSPC) logic in the frequency divider. Meanwhile, a novel balanced common-base structure is used in the frequency doubler design to widen the bandwidth and improve the fundamental rejection. The doubler shows a 41% fractional 3 dB bandwidths with a fundamental rejection better than 25.7 dB. The synthesizer has a maximum output power of 0 dBm with a DC power consumption of 60 mW. The worst phase noise at 100 kHz, 1 MHz and 10 MHz offset frequencies from the carrier is -71 dBc/Hz, -83 dBc/Hz and -102.4 dBc/Hz, respectively.

Citation


Jiankang Li, Yong-Zhong Xiong, Jin He, and Wen Wu, "A Q-Band Frequency Synthesizer in 0.13 μm SiGe BiCMOS ," Progress In Electromagnetics Research C, Vol. 47, 19-28, 2014.
doi:10.2528/PIERC13120408
http://jpier.org/PIERC/pier.php?paper=13120408

References


    1. Aluigi, L., L. Roselli, S. M. White, and F. Alimenti, "System-on-chip 36.8 GHz radiometer for space-based observation of solar flares: Feasibility study in 0.25 μm SiGe BiCMOS technology," Progress In Electromagnetics Research, Vol. 130, 347-368, 2012.
    doi:10.2528/PIER12061101

    2. Tien, C.-C., T.-M. M. Tien, and C. F. Jou, "A 802.11a pulse-swallow integer-N frequency synthesizer," Progress In Electromagnetics Research C, Vol. 7, 25-35, 2009.
    doi:10.2528/PIERC09021705

    3. Wu, T., X. Tang, and F. Xiao, "Design of a W-band stepped-frequency synthesizer with fast frequency switching," Journal of Infrared, Millimeter and Terahz Waves, Vol. 30, No. 8, 826-834, 2009.
    doi:10.1007/s10762-009-9517-3

    4. Shie, C.-I., J.-C. Cheng, S.-C. Chou, and Y.-C. Chiang, "Design of CMOS quadrature VCO using on-chip trans-directional couplers," Progress In Electromagnetics Research, Vol. 106, 91-106, 2010.
    doi:10.2528/PIER10053002

    5. Jang, S.-L., D. A. Tu, C.-W. Chang, and M.-H. Juang, "A low power push-push differential VCO using current-reuse circuit design technique," Progress In Electromagnetics Research C, Vol. 27, 85-97, 2012.
    doi:10.2528/PIERC11101806

    6. Mou, S., K. Ma, K. S. Yeo, N. Mahalingam, and B. K. Thangarasu, "A compact size low power and wide tuning range VCO using dual-tuning LC tanks," Progress In Electromagnetics Research C, Vol. 25, 81-91, 2012.
    doi:10.2528/PIERC11091308

    7. Cao, C. and K. O. Kenneth, "A power efficient 26 GHz 32 : 1 static frequency divider in 130nm bulk CMOS," IEEE Microwave and Wireless Components Letters, Vol. 15, No. 11, 721-723, 2005.
    doi:10.1109/LMWC.2005.858998

    8. Lee, J.-Y., S.-H. Lee, H. Kim, and H.-K. Yu, "A 28.5-32 GHz fast settling multichannel PLL synthesizer for 60 GHz WPAN radio," IEEE Transactions on Microwave Theory and Techniques, Vol. 56, No. 5, 1234-1246, 2008.
    doi:10.1109/TMTT.2008.920179

    9. Lam, C. and B. Razavi, "A 2.6 GHz/5.2 GHz frequency synthesizer in 0.4 μm CMOS technology," IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, 788-794, 2000.
    doi:10.1109/4.841508

    10. Wang, L., Y.-Z. Xiong, B. Zhang, S.-M. Hu, and T.-G. Lim, "Millimeter-wave frequency doubler with transistor grounded-shielding structure in 0.13 μm SiGe BiCMOS technology," IEEE Transactions on Microwave Theory and Techniques, Vol. 59, No. 5, 1304-1310, 2011.
    doi:10.1109/TMTT.2011.2105276

    11. Li, J., L. Zhong, Y.-Z. Xiong, D. Hou, R.Wang, W. L. Goh, and W.Wu, "A PAE of 17.5% Ka-band balanced frequency doubler with conversion gain of 20 dB," 2012 IEEE Radio Frequency Integrated Circuits Symposium, 345-348, 2012.
    doi:10.1109/RFIC.2012.6242296

    12. Hung, J. J., T. M. Hancock, and G. M. Rebeiz, "High-power high-efficiency SiGe Ku- and Ka-band balanced frequency doublers," IEEE Transactions on Microwave Theory and Techniques, Vol. 53, No. 2, 754-761, 2005.
    doi:10.1109/TMTT.2004.840615

    13. Chen, J. H. and H. wang, "A high gain, high power k-band frequency doubler in 0.18 μm CMOS Process," IEEE Microwave and Wireless Components Letters, Vol. 20, No. 9, 522-524, 2010.
    doi:10.1109/LMWC.2010.2057412

    14. Chen, A. Y. K., Y. Baeyens, Y. K. Chen, and J. Lin, "A 36-80 GHz high gain millimeter-wave double-balanced active frequency doubler in SiGe BiCMOS," IEEE Microwave and Wireless Components Letters, Vol. 19, No. 9, 572-574, 2009.
    doi:10.1109/LMWC.2009.2027084

    15. Lin, K. Y., J. Y. Huang, C. K. Hsieh, and S. C. Shin, "A broadband balanced distributed frequency doubler with a sharing collector line," IEEE Microwave and Wireless Components Letters, Vol. 19, No. 2, 110-112, 2009.
    doi:10.1109/LMWC.2008.2011336

    16. He, , J., , J. Li, D. Hou, Y.-Z. Xiong, D. L. Yan, M. A. Arasu, and M. Je, "A 20 GHz VCO for PLL synthesizer in 0.13-μm BiCMOS," 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 231-233, 2012.
    doi:10.1109/RFIT.2012.6401670

    17. Li, J., Y.-Z. Xiong, S. Hu, W. L. Goh, D. Hou, and W. Wu, "Performance analyse on millimetre-wave bonding-wire interconnection," IEEE Electrical Design for Advanced Packaging and Systems Symposium, 1-4, 2010.

    18. Jain, V., B. Javid, and P. Heydari, "A BiCMOS dual-band millimeter-wave frequency synthesizer for automotive radars," IEEE Journal of Solid-State Circuits, Vol. 44, No. 8, 2100-2113, 2009.
    doi:10.1109/JSSC.2009.2022299

    19. Pellerano, , S., , R. Mukhopadhyay, A. Ravi, J. Laskar, Y. Palaskas, and , "A 39.1-to-41.6 GHz ΔΣ fractional-N frequency synthesizer in 90nm CMOS," IEEE International Solid-State Circuits Conference, 2008.

    20. Richard, O., A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, and P. Urard, "A 17.5-to-20.94 GHz and 35-to-41.88 GHz PLL in 65nm CMOS for wireless HD applications," IEEE International Solid-State Circuits Conference, 2010.