Compact K-Band CMOS baluns are designed, fabricated and characterized in a 130 nm CMOS technology. These baluns include a tunable active balun, a L-C lumped element balun, and two asymmetric planar transformer baluns. The detailed design processes are presented, including the topology selection, the transistor, inductor and transformer sizing, and the layout considerations. These topologies are compared in various aspects such as insertion loss, phase and amplitude imbalance, bandwidth, chip area, power consumption, and the difficulty to design and integration. An impedance tuning approach is implemented to chose the proper balun topology and to simply the balun integration. The baluns are on-wafer characterized and the measurement results compare the state-of-the-art realizations..
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