1. International Technology Roadmap for Seminconductors Update Overview, http://www.itrs.net/Links/2009ITRS/Home2009.htm.
2. Deutsch, A., "High-speed signal propagation on lossy transmission lines," IBM J. Res. Develop., Vol. 34, No. 4, 601-615, Jul. 1990.
doi:10.1147/rd.344.0601
3. Celik, M., L. Pileggi, and A. Odabasioglu, , IC Interconnect Analysis, 1-4020-7075-6, Kluwer Academic Publisher, 2002.
4. Ligocka-Wardzinska, A. and W. Bandurski, "Sensitivity of output response to geometrical dimensions in VLSI interconnects," Proc. of 13th IEEE Workshop SPI, 1-4, Strasbourg, France, May 2009.
5. Chiu, C.-N. and I.-T. Chiang, "A fast approach for simulating long-time response of high-speed dispersive and lossy interconnects terminated with nonlinear loads," Progress In Electromagnetics Research, Vol. 91, 153-171, 2009.
doi:10.2528/PIER09021502
6. Ghoneima, M., Y. Ismail, M. M. Khellah, J. Tschanz, and V. De, "Serial-link bus: A low-power on-chip bus architecture," IEEE Trans. CAS I, Vol. 56, No. 9, 2020-2032, Sep. 2009.
doi:10.1109/TCSI.2008.2010155
7. Hwang, M.-E., S.-O. Jung, and K. Roy, "Slope interconnect effort: Gate-interconnect interdependent delay modeling for early CMOS circuit simulation," IEEE Trans. CAS I, Vol. 56, No. 7, 1428-1441, Jul. 2009.
8. Elmore, W. C., "The transient response of damped linear networks," J. Appl. Phys., Vol. 19, 55-63, Jan. 1948.
doi:10.1063/1.1697872
9. Wyatt, J. L., Circuit Analysis, Simulation and Design, Elsiever Science, 1978.
10. Kahng, A. B. and S. Muddu, "An analytical delay model of RLC interconnects," IEEE Trans. Computed-Aided Design, Vol. 16, 1507-1514, Dec. 1997.
doi:10.1109/43.664231
11. Ismail, Y. I. and E. G. Friedman, "Effects of inductance on the propagation, delay and repeater insertion in VLSI circuits," IEEE Trans. VLSI Sys., Vol. 8, No. 2, 195-206, Apr. 2000.
doi:10.1109/92.831439
12. Ismail, Y. I., E. G. Friedman, and J. L. Neves, "Equivalent Elmore delay for RLC trees," IEEE Trans. CAD, Vol. 19, No. 1, 83-97, Jan. 2000.
13. Ligocka, A. and W. Bandurski, "Effect of inductance on interconnect propagation delay in VLSI circuits," Proc. of 8th IEEE Workshop SPI, 121-124, May 9--12, 2004.
14. Basl, P. A. W., M. H. Bakr, and N. K. Nikolova, "Efficient transmission line modeling sensitivity analysis exploiting rubber cells," Progress In Electromagnetics Research B, Vol. 11, 223-243, 2009.
doi:10.2528/PIERB08111502
15. Xie, H., J. Wang, R. Fan, and Y. Liu, "Study of loss effect of transmission lines and validity of a Spice model in electromagnetic topology," Progress In Electromagnetics Research, Vol. 90, 89-103, 2009.
doi:10.2528/PIER08121605
16. Hammerstad, E. and O. Jensen, "Accurate models for microstrip computer aided design," IEEE Trans. MTT, 407-409, 1980.
17. Hammerstad, E. O., "Equations for microstrip circuit design," Proc. of 5th EuMC, 268-272, Sep. 1975.
18. Marks, R. B. and D. F. Williams, "Interconnection transmission line parameter characterization," Proc. of 40th ARTG Conf. Dig., 88-95, Orlando, FL, USA, Dec. 1992.
19. Marks, R. B. and D. F. Williams, "Characteristic impedance determination using propagation constant measurement," IEEE Mic. Guided Wave Lett., Vol. 6, 141-143, Jun. 1991.
doi:10.1109/75.91092
20. Eisenstadt, W. R. and Y. Eo, "S-parameter-based IC interconnect transmission line characterization," IEEE Trans. Comp. Hybrids Manuf. Technol., Vol. 15, 483-490, Aug. 1992.
doi:10.1109/33.159877
21. Deutsch, A., R. S. Krabbenhoft, K. L. Melde, C. W. Surovicm, G. A. Katopis, G. V. Kopcsay, Z. Zhou, Z. Chen, Y. H. Kwark, T.-M. Winkel, X. Gu, and T. E. Standaert, "Application of the short-pulse propagation technique for broadband characterization of PCB and other interconnect technologies," IEEE Trans. EMC, Vol. 52, 266-287, Feb. 2010.
22. Cong, J., L. He, C.-K. Koh, and P. Madden, "Performance optimization of VLSI interconnect," Integration VLSI J., Vol. 21, 1-94.
doi:10.1016/S0167-9260(96)00008-9
23. Yun, B. and S. S. Wong, "Optimization of driver preemphasis for on-chip interconnects," IEEE Trans. CAS I, Vol. 56, No. 9, 2033-2041.
24. Rosenfeld, J. and E. G. Friedman, "Design methodology for global resonant H-tree clock distribution networks," IEEE Trans. VLSI Systems, Vol. 15, No. 2, 135-148, Feb. 2007.
doi:10.1109/TVLSI.2007.893576
25. Awwad, F. R., M. Nekili, V. Ramachandran, and M. Sawan, "On modeling of parallel repeater-insertion methodologies for SoC interconnects," IEEE Trans. CAS I, Vol. 55, No. 1, 322-335, Feb. 2008.
doi:10.1109/TCSI.2007.910538
26. Ravelo, B., A. Perennec, and M. Le Roy, "Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology," Proc. of 13th IEEE Workshop SPI, Strasbourg, France, May 2009.
27. Ravelo, B., A. Perennec, and M. Le Roy, "New technique of inter-chip interconnect effects equalization with negative group delay active circuits," VLSI, Vol. 20, 409-434, Z. F. Wang (ed.), INTECH, Feb. 2010.
28. Zhang, J. and T. Y. Hsiang, "Extraction of subterahertz transmission-line parameters of coplanar waveguides," PIERS Online, Vol. 3, No. 7, 1102-1106, 2007.
doi:10.2529/PIERS060912144405
29. Kashyap, C. V., C. J. Alpert, F. Liu, and A. Devgan, "Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees," IEEE Trans. CADICAS I, Vol. 23, No. 4, 509-516, Apr. 2004.
30. Kirschning, M. and R. H. Jansen, "Accurate model for effective dielectric constant with validity up to millimeter-wave frequencies," Electronics Letters, Vol. 18, 272-273, 1982.
doi:10.1049/el:19820186
31. Pozar, D. M., Microwave Engineering, 2nd Ed., 9-21, John Wiley, 1998.
32. Pucel, R. A., D. J. Massé, and C. Hartwing, "Losses in microstip," IEEE Trans. MTT, Vol. 16, No. 6, 342-350, 1968.
doi:10.1109/TMTT.1968.1126691
33. Chen, C., J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis, Wiley, 2000.
34. Zhang, G. H., M. Y. Xia, and X. M. Jiang, "Transient analysis of wire structures using time domain integral equation method with exact matrix elements," Progress In Electromagnetics Research, Vol. 92, 281-298, 2009.
doi:10.2528/PIER09032003
35. Torrungrueng, D. and S. Lamultree, "Equivalent graphical solutions of terminated conjugately characteristic-impedance transmission lines with non-negative and corresponding negative characteristic resistances," Progress In Electromagnetics Researc, Vol. 92, 137-151, 2009.
doi:10.2528/PIER09031001
36. Roy, A., S. Ghosh, and A. Chakrabarty, "Simple crosstalk model of three wires to predict near-end and far-end crosstalk in EMI/EMC environment to facilitate EMI/EMC modeling," Progress In Electromagnetics Research B, Vol. 8, 43-58, 2008.
doi:10.2528/PIERB08050503