volume | PIER Journals

2019-06-13

Suppression of IMD3 in CMOS Power Amplifier Using Bias Circuit of Common-Gate Transistor with Cascode Structure

Jinwon Kim,

Dr. Jinwon Kim

School of Electronic Engineering

Soongsil University

Korea

Homepage

Changhyun Lee,

Dr. Changhyun Lee

College of Information Technology

Soongsil University

Republic of Korea

Homepage

Jinho Yoo,

Dr. Jinho Yoo

School of Electronic Engineering

Soongsil University

Republic of Korea

Homepage

Changkun Park

Dr. Changkun Park

School of Electronic Engineering

Soongsil University

South Korea

Homepage

Progress In Electromagnetics Research M, Vol. 82, 1-8, 2019

doi:10.2528/PIERM19041105

Abstract

In this study, we propose a technique to improve the linearity of complementary metal-oxide semiconductor (CMOS) power amplifiers with a cascode structure. From the investigation of the influence of the impedance of an envelope signal on the linearity, we find that the load impedance of the envelope signal of the common-source transistor should be reduced. To obtain alow load impedance of the envelope signal, we reduce the value of the gate resistor of the common-gate transistor. After investigating the influences of the value of the resistance on the third-order intermodulation distortion (IMD3), we extract the optimum value of the resistance. We also consider the electrostatic discharge protection issue and the effects of the variations in the parasitic components of bond-wires, in the process of the extraction of the optimum value. To verify the feasibility of the optimization technique of the resistance ofthe bias circuit of the common-gate transistor of the amplifier, we design a power amplifier using a 180-nm RFCMOS process for wireless local area network (WLAN) 802.11n applications. We obtain the measured maximum linear output power of 22.2 dBm with a 26.7% power-added efficiency and a 3.72% error vector magnitude. We use an 802.11n modulated signal with 64-QAM (MCS7) at 65 Mb/s. From the measured results, we successfully verify the feasibility of the proposed optimization technique of the resistance of the bias circuit of the common-gate transistor.

Citation

Copy Export

Jinwon Kim, Changhyun Lee, Jinho Yoo, and Changkun Park, "Suppression of IMD3 in CMOS Power Amplifier Using Bias Circuit of Common-Gate Transistor with Cascode Structure," Progress In Electromagnetics Research M, Vol. 82, 1-8, 2019.
doi:10.2528/PIERM19041105

References

1. Lim, W., et al. "Dual-mode CMOS power amplifier based on load-impedance modulation," IEEE Microw. Wirel. Compon. Lett., Vol. 28, 1041-1043, 2018.
doi:10.1109/LMWC.2018.2871339

2. Jeong, G., T. Joo, and S. Hong, "A highly linear and efficient CMOS power amplifier with cascode-cascade configuration," IEEE Microw. Wirel. Compon. Lett., Vol. 27, 596-598, 2017.
doi:10.1109/LMWC.2017.2701327

3. Kang, S., G. Jeong, and S. Hong, "Study on dynamic body bias controls of RF CMOS cascode power amplifier," IEEE Microw. Wirel. Compon. Lett., Vol. 28, 705-707, 2018.
doi:10.1109/LMWC.2018.2849209

4. Kang, S., D. Baek, and S. Hong, "A 5-GHz WLAN RF CMOS power amplifier with a parallel-cascoded configuration and an active feedback linearizer," IEEE Trans. Microw. Theory Techn., Vol. 65, 3230-3244, 2017.
doi:10.1109/TMTT.2017.2691766

5. Park, J., C. Lee, and C. Park, "A quad-band CMOS linear power amplifier for EDGE applications using an anti-phase method to enhance its linearity," IEEE Trans. Circuits Syst. I - Regul. Pap., Vol. 64, 765-776, 2017.
doi:10.1109/TCSI.2016.2620559

6. Park, J., C. Lee, J. Yoo, and C. Park, "A CMOS antiphase power amplifier with an MGTR technique for mobile applications," IEEE Trans. Microw. Theory Techn., Vol. 65, 4645-4656, 2017.
doi:10.1109/TMTT.2017.2709304

7. Jin, S., M. Kwon, K. Moon, B. Park, and B. Kim, "Control of IMD asymmetry of CMOS power amplifier for broadband operation using wideband signal," IEEE Trans. Microw. Theory Techn., Vol. 61, 3753-3762, 2013.
doi:10.1109/TMTT.2013.2280116

8. Jung, S.-C., et al. "A new envelope predistorter with envelope delay taps for memory effect compensation," IEEE Trans. Microw. Theory Techn., Vol. 55, 52-59, 2007.
doi:10.1109/TMTT.2006.886909

9. Joo, T., B. Koo, and S. Hong, "A WLAN RF CMOS PA with large signal MGTR method," IEEE Trans. Microw. Theory Techn., Vol. 61, 1272-1279, 2013.
doi:10.1109/TMTT.2013.2244228

10. Joo, T., B. Koo, and S. Hong, "A WLAN RF CMOS PA with adaptive power cells," Proc. IEEE RFIC Symp., 345-348, Seattle, WA, USA, 2013.

11. Kaymaksut, E. and P. Reynaert, "Transformer based uneven Doherty power amplifier in 90 nm CMOS for WLAN applications," IEEE J. Solid-State Circuits, Vol. 47, 1659-1671, 2012.
doi:10.1109/JSSC.2012.2191334

12. Yin, Y., X. Yu, Z. Wang, and B. Chi, "An efficiency-enhanced stacked 2.4-GHz CMOS power amplifier with mode switching scheme for WLAN applications," IEEE Trans. Microw. Theory Techn., Vol. 63, 672-682, 2015.
doi:10.1109/TMTT.2014.2387838

13. Jeong, G., S. Kang, T. Joo, and S. Hong, "An integrated dual-mode CMOS power amplifier with linearizing body network," IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 64, 1037-1041, 2017.
doi:10.1109/TCSII.2016.2624302

14. Jin, Y. and S. Hong, "A 2.4-GHz CMOS common-gate combining power amplifier with load impedance adaptor," IEEE Microw. Wirel. Compon. Lett., Vol. 27, 836-838, 2017.
doi:10.1109/LMWC.2017.2734748

15. Ahn, H., S. Baek, I. Nam, D. An, J. K. Lee, M. Jeong, B.-E. Kim, J. Choi, and O. Lee, "A fully integrated dual-mode CMOS power amplifier with an autotransformer-based parallel combining transformer," IEEE Microw. Wirel. Compon. Lett., Vol. 27, 833-835, 2017.
doi:10.1109/LMWC.2017.2734762

16. Yoo, J., C. Lee, I. Kang, and C. Park, "2.4-GHz CMOS linear power amplifier for IEEE 802.11n WLAN applications," Microw. Opt. Technol. Lett., Vol. 59, 546-550, 2017.
doi:10.1002/mop.30343