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2017-07-26

A 6.6 GHz Quadrature Frequency Synthesizer with -78 Dbc Reference Spur for UWB Application

By Minghua Wang, Xiaosong Wang, Yu Liu, and Haiying Zhang
Progress In Electromagnetics Research C, Vol. 76, 63-73, 2017
doi:10.2528/PIERC17032301

Abstract

An integer-N quadrature frequency synthesizer for single-band UWB application was designed in 0.18 μm CMOS technology. A modified bottom-series quadrature voltage-controlled oscillator (QVCO) based on reconfigurable LC tank is employed to provide quadrature signals and cover a range from 6.48 GHz to 7.07 GHz. In order to suppress the reference spur levels, an improved charge-averaging charge pump and a highly linear phase-frequency detector (PFD) are used. From the carrier of 6.6 GHz, the measured reference spur is -78.2 dBc, and the measured phase noise is -115.4 dBc/Hz at 1MHz offset. The frequency synthesizer including buffers consumes a total power of 99 mW from a 1.8 V power supply. Chip size is 1.6 mm×0.9 mm.

Citation


Minghua Wang, Xiaosong Wang, Yu Liu, and Haiying Zhang, "A 6.6 GHz Quadrature Frequency Synthesizer with -78 Dbc Reference Spur for UWB Application," Progress In Electromagnetics Research C, Vol. 76, 63-73, 2017.
doi:10.2528/PIERC17032301
http://jpier.org/PIERC/pier.php?paper=17032301

References


    1. Liang, C., et al., "A 14-band frequency synthesizer for MB-OFDM UWB application," IEEE ISSCC Dig. Tech. Papers, 126-127, Feb. 2006.

    2. Zhang, J., et al., "An improved charge-averaging charge pump for a fractional-N frequency synthesizer," Chinese Journal of Semiconductors, Vol. 29, No. 5, 913-916, 2008.

    3. Wang, X., et al., "A wideband frequency synthesizer for a receiver application at multiple frequencies," Chinese Journal of Semiconductors, Vol. 31, No. 3, 035003-1-5, 2010.

    4. Zhang, G., "Linear Phase Frequency Detector and Charge Pump for Phase-Locked Loop,", Chinese Patent, 200780044070.5, 2007-11-27.

    5. Zhang, Y., et al., "A low-phase noise LC QVCO with bottom-series coupling and capacitor tapping," Proc. IEEE ISCAS, 1000-1003, May 2008.

    6. Lanka, N., et al., "A sub-2.5 ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology," IEEE CICC, 57-60, Sep. 2009.

    7. Li, Z., et al., "A programmable 2.4GHz CMOS multi-modulus frequency divider," Chinese Journal of Semiconductors, Vol. 29, No. 2, 224-228, 2008.

    8. Vaucher, C. S., et al., "A family of low-power truly modular programmable dividers in standard 0.35 μm CMOS technology," IEEE Journal of Solid-State Circuits, Vol. 35, 1039-1045, 2000.
    doi:10.1109/4.848214

    9. Rogers, J., et al., "Integrated circuit design for high-speed frequency synthesis,", 2006.

    10. Rategh, H. R., et al., "A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver," IEEE Journal of Solid-State Circuits, Vol. 35, 780-787, 2000.
    doi:10.1109/4.841507

    11. Zheng, H. and C. L. Howard, "A 1.5V 3.1GHz–8 GHz CMOS synthesizer for 9-band MB-OFDM UWB transceivers," IEEE J. Solid-State Circuits, Vol. 42, No. 6, 1250-1260, Jun. 2008.
    doi:10.1109/JSSC.2007.897135

    12. Huang, Z.-D., et al., "A 1.5-V 3 ∼ 10 GHz 0.18-μm CMOS frequency synthesizer for MB-OFDM UWB applications," IEEE MTT-S International Microwave Symposium Digest, 229-232, Jun. 2008.

    13. Lu, T.-Y. and W.-Z. Chen, "A 3–10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system," IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol. 20, 948-958, 2012.
    doi:10.1109/TVLSI.2011.2134874

    14. Li, W., et al., "Asingle inductor approach to the design of low-voltage CMOS MB-OFDM UWB frequency synthesizer," IEEE MTT-S International Microwave Symposium Digest, 1-3, 2012.

    15. Lo, Y.-C., et al., "A 0.6 ps jitter 2–16 GHz 130 nm CMOS frequency synthesizer for broadband applications," IEEE International Symposium on Circuits and Systems (ISCAS), 3048-3051, 2015.

    16. Kim, J., et al., "A 44GHz differentially tuned VCO with 4GHz tuning range in 0.12 μm SOI CMOS," IEEE International Digest of Technical Papers. Solid-State Circuits Conference, Vol. 1, 416-607, San Francisco, CA, 2005.

    17. Ikeda, S., et al., "A 0.5V 5.96-GHz PLL with amplitude-regulated current-reuse VCO," IEEE Microwave and Wireless Components Letters, Vol. 27, No. 3, 302-304, Mar. 2017.
    doi:10.1109/LMWC.2017.2662001

    18. Chang, H.-Y., et al., "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL withself-aligned DLL in 65-nm CMOS technology," IEEE Trans. Microw. Theory Tech., Vol. 62, No. 3, 543-555, Mar. 2014.
    doi:10.1109/TMTT.2014.2302747

    19. El-Halwagy, W., et al., "A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture," IEEE Transactions on Microwave Theory and Techniques, Vol. 65, No. 2, 396-413, Feb. 2017.
    doi:10.1109/TMTT.2016.2647698