This paper demonstrates the exhibition of pulse compression from an electronic circuit with negative group delay (NGD). This circuit consists of a field effect transistor (FET) cascaded with shunt RLC network. Theoretic and experimental investigations have proved that, at its resonance frequency, the group delay of this circuit is always negative. The present study shows that around this resonance, it presents a gain form enabling to generate pulse compression. To validate this concept, as proof-of-principle, devices with one- and two-stages FET were implemented and tested. Measurements of the one-stage test device evidenced an NGD of about -2.5 ns and simultaneously with 2 dB amplification operating at 622 MHz resonance frequency. In the frequency domain, in the case of a Gaussian input pulse with 40\,MHz frequency standard deviation, this resulted in 125% expansion of pulse width compared to the input one. In time domain, simulations showed that the compression was about 80% in the case of an input Gaussian pulse with 4 ns standard deviation. With the other prototype comprised of two-stage NGD cell, the use of a sine carrier of about 1.03 GHz allowed to achieve 87% pulse width compression.
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