Vol. 5

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2008-03-18

A 2.3-MW 16.7-MHz Analog Matched Filter Circuit for DS-CDMA Wireless Applications

By Mostafa El-Tokhy and H. A. Mansour
Progress In Electromagnetics Research B, Vol. 5, 253-264, 2008
doi:10.2528/PIERB08022406

Abstract

The matched filter (MF) is known as the fastest method for acquisition of DS-CDMA signals. Power consumption of the MF is a key issue for realizing multimedia hand-held terminals. We proposed a new Analog Matched Filter using Sample-and-Hold (S/H) circuit, which performs correlation between an input signal and a filtering coefficient employed for modulation in fully analog domain, eliminating the need to Analog-to-digital (A/D) conversion, so reduces power consumption and chip area. Simulation results reveal that the proposed circuit dissipates 2.3 mW power consumption at a chip rate of 16.7 MHz with 3.3 V power supply for 15 taps configuration. The proposed analog architecture could improve the performance of mobile terminals.

Citation


Mostafa El-Tokhy and H. A. Mansour, "A 2.3-MW 16.7-MHz Analog Matched Filter Circuit for DS-CDMA Wireless Applications," Progress In Electromagnetics Research B, Vol. 5, 253-264, 2008.
doi:10.2528/PIERB08022406
http://jpier.org/PIERB/pier.php?paper=08022406

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