Since the system-level package was proposed, the electronics industry has increasingly attached importance to both directly relevant and related issues, and the scope of system-level package use has increased. Creating more complex system-level package structures, thereby leading to the design of overall electrical effects, requires more electromagnetic simulation resources, and therefore a great deal of time in the design process. The main purpose of this paper is to analyze the effects of system-level packaging, and to establish systems-in-package in accordance with electrical specifications. Using a segmented approach, this paper also builds an overall model for designers to predict electrical characteristics, thus shortening the product development schedule. In this paper, the transmission effects of a substrate are analyzed by changing the length of the substrate transmission line, with or without a thermal ground ball and ground ring. Previously established package IP are cascaded to establish the model of the package substrate, which verifies the feasibility of the package IP. We then analyze the characteristics of the interference between chips and package using an integrated passive device, and propose a complete package equivalent circuit model.
2. Chen, C.-C., C.-H.Wang, B.-J. Huang, H.-W. Tsao, and H.Wang, "A 24-GHz divide-by-4 injection-locked frequency divider in 0.13-μm CMOS technology ," IEEE Asian Solid-State Circuits Conference, ASSCC'07, 340-343, 2007.
3. Villegas, A., D. Vaquez, and A. Rueda, "A low power low voltage mixer for 2.4 GHz applications in CMOS-90nm technology," IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 44-47, 2010.
4. Siligaris, A., N. Deparis, R. Pilard, D. Gloria, C. Loyez, N. Rolland, L. Dussopt, J. Lanteri, R. Beck, and P. Vincent, "A 60 GHz UWB impulse radio transmitter with integrated antenna n CMOS 65nm SOI technology," IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 153-156, 2011.
5. Popp, J. D., B. Kormanyos, M. Adams, A. Hurtado, J. Braatz, C. Wolfhausen, and T. McKay, "Design of millimeter-wave mixed signal circuits in 45nm SOI CMOS," IEEE International SOI Conference (SOI), 1-2, 2010.
6. Tan, Y., H. Xu, M. A. El-tanani, S. Taylor, and H. Lakdawala, "A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 426-428, 2011.
7. Kuhn, K. J., "CMOS scaling for the 22nm node and beyond: Device physics and technology," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 1-2, 2011.
8. Eshraghian, K., "SoC emerging technologies," Proceedings of the IEEE, Vol. 94, No. 6, 1197-1213, 2006.
9. Saleh, R., S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. P. Pande, C. Grecu, and A. Ivanov, "System-on-chip: Reuse and integration," Proceedings of the IEEE, Vol. 94, No. 6, 1050-1069, 2006.
10. Beelen-Hendrikx, C., "Trends in IC packaging," European Microelectronics and Packaging Conference, EMPC, 1-8, 2009.
11. Tummala, R. R., "Packaging: Past, present and future," 6th International Conference on Electronic Packaging Technology, 3-7, Mar. 2005.
12. Sham, M. X., Y. C. Chen, L. W. Leung, J. R. Lin, and T. Chung, "Challenges and opportunities in system-in-package (SiP) business," 7th International Conference on Electronic Packaging Technology, ICEPT'06, 1-5, 2006.
13. , , "Welcome to the IEEE International: 3D system integration conference (3DIC)," IEEE International 3D Systems Integration Conference (3DIC), 1-16, 2010.
14. Chen, M.-K., Y.-J. Huang, S.-J. Hou, Y.-H. Chen, C.-K. Yang, and S.-L. Fu, "Electrical modeling and circuit simulation for SI analysis of high-speed FC-BGA," International Conference on Electronic Materials and Packaging, EMAP 2006, 1-6, Dec. 11-14, 2006.
15. Jin, C.-Y., C.-H. Chou, D.-R. Li, and T.-Y. Chuang, "Improving signal integrity by optimal design of power/ground plane stack-up structure," 8th Electronics Packaging Technology Conference, EPTC'06, 853-859, Dec. 6-8, 2006.
16. Kaw, R., B. Hanna, and N. Devnani, "Comparison of electrical performance of enhanced BGA's," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 21, No. 2, 164-170, May 1998.
17. Yazdani, F., "Signal integrity characterization of microwave XFP ASIC BGA package realized on low-K liquid crystal polymer (LCP) substrate," IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, 359-363, May 2006.
18. Horng, T. S., A. Tseng, H. H. Huang, S. M. Wu, and J. J. Lee, "Comparison of advanced measurement and modeling techniques for electrical characterization of ball grid array packages," 48th IEEE Electronic Components & Technology Conference, 1464-1471, May 25-28, 1998.
19. Horng, T. S., S. M. Wu, J. Y. Li, C. T. Chiu, and C. P. Hung, "Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages," 50th Electronic Components & Technology Conference, 439-444, 2000.
20. Horng, T. S., S. M. Wu, and C. Shih, "Electrical modeling of RFIC packages up to 12 GHz," 49th Electronic Components and Technology Conference, 867-872, 1999.
21. Lion, L. L., M. Y. Muh, and A. Ferendeci, "Equivalent circuit parameter extraction of microstrip coupling lines using FDTD method," IEEE Antennas and Propagation Society International Symposium, Vol. 3, 1488-1491, Jul. 16-21, 2000.
22. Wu, S.-M., C.-T. Kuo, and C.-H. Chen, "Very compact full differential bandpass filter with transformer integrated using integrated passive device technology," Progress In Electromagnetics Research, Vol. 113, 251-267, 2011.
23. Wu, S.-M., C.-T. Kuo, P.-Y. Lyu, Y.-L. Shen, and C.-I. Chien, "Miniaturization design of full differential bandpass filter with coupled resonators using embedded passive device technology," Progress In Electromagnetics Research, Vol. 121, 365-379, 2011.
24. Wai, L. L., K. M. Chua, A. C. W. Lu, M. Sun, and Y.-P. Zhang, "A compact package with integrated patch antenna for single-chip 60-GHz radios," Progress In Electromagnetics Research C, Vol. 20, 227-238, 2011.
25. Kaupp, H. R., "Characteristics of microstrip transmission lines," IEEE Transactions on Electronic Computers, Vol. 16, No. 2, 185-193, Apr. 1967.
26. Nelatury, S. R., M. N. O. Sadiku, and V. K. Devabhaktuni, "CAD models for estimating the capacitance of a microstrip interconnect: Comparison and improvisation," PIERS Proceedings, 18-23, Prague, Czech Republic, Aug. 27-30, 2007.
27. Johnson, H. and M. Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993.